The present invention relates generally to the protection of integrated circuits against electrostatic discharge (ESD) voltage events and, more particularly, to a lower trigger voltage ESD protection transistor for integrated circuits.
The progression of integrated circuit technology has led to the scaling of transistors to enable faster transistors operating at lower supply voltages. In complementary metal oxide semiconductor (CMOS) applications, the faster transistors require the use of very thin gate oxides and shorter channel lengths in order to obtain higher drive currents. The gate oxide thickness, for instance, has decreased from approximately 5.0 nanometers (nm) in 0.25 micron (μm) technology to approximately 1.5 nm in 90 nm technology, and is expected to decrease even further in future technologies. The thinner gate oxides are more susceptible to failure under random ESD voltages due to their smaller breakdown voltages.
The problem of ESD voltage events occurring on input/output (I/O) pins to the integrated circuit has been addressed in many ways. Most common is the use of an ESD protection device connected to the input/output pad of an integrated circuit to safely discharge ESD currents to ground before they can damage any of the connected circuitry. ESD events may be generally characterized by a human body model (HBM), a charged device model (CDM), or a machine model (MM). Different ESD models correspond to different current pulse waveforms and different peak currents.
One of the more common devices for protecting the integrated circuits from ESD events is the use of an n-type, metal oxide semiconductor field effect transistor (NMOSFET, or NFET for short), which, when connected to the input/output connection, discharges the current produced from an ESD event to ground. Depending upon the polarity of the ESD event, the, NFET-based ESD protection device operates either as a lateral NPN bipolar junction transistor (NPN BJT) or as a diode. During an electrically positive ESD event, where the voltage on the input/output pin to which the NFET is connected spikes positive with respect to ground, the NFET device operates as a BJT to quickly dissipate the ESD current to ground. During an electrically negative ESD event, where the potential on the input/output pin spikes negative with respect to ground, the NFET operates as a diode to discharge the ESD current to ground.
The smaller breakdown voltage of the thin gate oxides and the decreasing junction breakdown voltages in the state of the art CMOS devices require that the ESD protection devices turn on and operate at voltages lower than the gate oxide or junction breakdown to enable adequate ESD protection.